Dynamic Random Access Memory (DRAM) memory cells are basically charge-storage capacitors with driver transistors. In other words, data is stored on a tiny capacitor within each memory cell. The presence or absence of charge in a capacitor is interpreted by the DRAM's sense line as a logical 1 or 0.
Because of a charge's natural tendency to distribute itself into a lower energy-state, however, DRAMs require periodic charge refreshing to maintain data storage. Stated differently, due to leakage the data may leak off after a period of time. To maintain data integrity, it is necessary to refresh each of the DRAM memory rows within this period of time. A refresh operation generally comprises copying the data held in the memory cells into one or more registers and then copying the data in the registers back into the memory cells.
Traditionally, this refresh requirement has required additional circuitry to handle the DRAM subsystem refresh. And when refresh procedures made the DRAM unavailable for reading and writing the memory's control circuitry had to arbitrate for access.
It is common in the prior art for the memory control circuitry to intercede between read or write transactions in order to facilitate the refresh function. This unfortunately delays transactions which must wait while a refresh operation completes before being serviced.
The present invention facilitates the DRAM refresh function in a less obtrusive manner than in the prior art. This is accomplished by facilitating the refresh function during idle time when the DRAM is not busy handling read or write transactions. If insufficient idle time exists then the present invention will force a refresh operation thus ensuring that all memory cells are maintained in a properly charged state.